Due to an ever increasing demand for high speed components in electronic applications, the availability of high speed analog-to-digital (A/D) converters is becoming very important. High speed A/D converters are conventionally implemented using a flash architecture. Each comparator in a flash A/D compares reference voltages to the analog inputs. When the reference is more positive, the decision circuit outputs a 1 and when it is more negative, it outputs a zero (-1). The analog voltage is quantized by finding which two reference voltages the input voltage is between Although flash architecture A/D converters do provide speed, they also use 2.sup.n -1 comparators, where n is the bit-number accuracy. Thus, an 8-bit A/D converter uses 255 comparators. Likewise, a 9-bit A/D comparator uses 511 comparators, and a 10-bit A/D comparator uses 1023 comparators. The more logic gates used, the higher the power consumption, die size, and cost of the circuit. The parallel gates used in flash A/D's are a problem because, among other things, connecting these gates either loads the input with parasitic loading or uses a fanout approach which can cause the signals at the parallel sections of the chip to differ.
A/D converters rely on the values of their circuit components, typically resistors or capacitors, to form ratios that digitally represent the ratio of an input signal to a reference signal. As a result, the primary limitation on the accuracy that can be achieved with an A/D converter is the variation in the values of the components. This variation, known as component mismatch, causes these ratios to deviate from their nominal values, which, in turn, produces errors in the digital representation of the input signal.
An alternative arrangement to the flash architecture is known as a serial, or "pipelined", architecture. One such pipelined architecture technique is shown in U.S. Pat. No. 5,047,772 to Ribner. Ribner describes a basic sub-ranging A/D converter comprising two or more similar conversion stages connected together in a cascade arrangement. Each conversion stage includes a sample-and-hold (S/H) circuit to which an analog input signal is applied. Each stage uses a low resolution A/D converter to generate a binary conversion signal corresponding to the nearest quantized level below that of the analog input signal applied of the sample-and-hold circuit of that stage, while a companion D/A converter generates a quantized analog signal corresponding to the nearest quantized level below that of the analog input signal applied to the sample-and-hold circuit of that stage. This quantized analog signal in each stage is subtracted from the analog input signal in that stage. A subsequent gain amplifier in each stage boosts the residual signal in that stage back to a level consistent with the input range of the next stage. Thus, each stage digitally approximates its analog input signal and passes the remainder of that analog signal, after amplification, to the following stage for further processing. Normally, design dictates that the interstage gain be 2.sup.L for a stage with an L-bit A/D and D/A converter to boost the residual signal up to the full scale level of the following stage.
In a pipelined operation, the signal processed by each stage is delayed from the preceding stage by one sample period. Thus a latency of M-clock cycles or M-half clock cycles is desirably required before an output signal is available from the final stage. The output signals of earlier stages are available sooner and are delayed accordingly before being combined into a single output signal. The parallel outputs from each conversion stage are combined to produce a resultant binary output signal which represent the analog input signal to the multi-stage analog-to-digital converter.
Heretofore, high speed A/D conversions have not been achieved using pipelined architecture A/D converters because a sampling circuit, utilized in each pipeline stage, which provides a high input tracking bandwidth, minimal sampling aperture, and minimal sampling errors has not been available. The tracking bandwidth is the speed at which the sampling circuit can track its input. Sampling aperture is the time the circuit responds to the input after it is switched to a holding mode. Settling time is the time the circuit rings after switching. The circuit is capable of ringing for some time after it no longer responds to the input. Sampling a high frequency input desirably requires a high tracking bandwidth and a short sampling aperture. The sampling aperture can also be expressed as a sampling aperture bandwidth. The sampling aperture bandwidth is the equivalent bandwidth of integrating the input signal during the sampling aperture time and is equal to 1/(2* Sample Aperture Time). To track and hold a high frequency signal, both the tracking bandwidth and the sampling aperture bandwidths are higher than the bandwidth of the signal being sampled.
To achieve the bandwidth, sampling aperture and sampling error requirements for a high speed A/D converters, the sampling circuits used to implement it are desirably highly linear to achieve very low sampling error rates. One reason such a sampling circuit has been difficult to implement is that the components available to implement the sampling circuit, namely, bipolar NPN transistors, resistors and capacitors, are inherently non-linear and switch from high to low and low to high asymmetrically.
Accordingly, a need exists for a pipelined architecture A/D converter which operates at high speeds, consumes minimal power and occupies minimal die space. A need also exists for a sampling circuit which provides high bandwidth, low sampling aperture, and low sampling error rates.